Example embodiments relate to frequency synthesizing, and more particularly to a frequency divider, a frequency synthesizer including the frequency divider, and an application circuit including the frequency synthesizer.
Phase-locked loop (PLL) circuits are widely used to synthesize a desired signal frequency. PLL frequency synthesizers typically employ an integer-N technique and a fractional-N technique. The integer-N technique uses a fixed integer N to divide an output frequency, and the fractional-N technique uses a number N to divide the output frequency which is selected among two or more integers (e.g., N is varied between two or more integers such that the average value of N is fractional). As a result, a divisor is fractional when using the fractional-N technique due to interpolation of each number N selected for each dividing operation.
It may be difficult to meet certain specifications when employing the integer-N technique due to a trade-off between loop bandwidth and channel spacing. The fractional-N technique alleviates such design restrictions on PLLs permitting a broader loop bandwidth while maintaining narrow channel intervals.
However, the fractional-N technique results in the generation of fractional spurs. In order to reduce the occurrence of fractional spurs, a frequency synthesizer incorporating a sigma/delta modulator has been employed. However, frequency synthesizers incorporating sigma/delta modulators suffer from the generation of so-called sigma/delta noise (e.g., a quantization noise).